1. Field of the Invention
The present invention relates to the structure of semiconductor devices and manufacturing methods thereof, and particularly to the structure of a gate insulating film of an insulated-gate transistor such as an MOS transistor.
2. Description of the Background Art
 less than MOS Transistor Structure greater than 
FIG. 30 is a sectional view showing the structure of a conventional MOS transistor. As shown in this diagram, the MOS transistor is fabricated in the transistor formation region between element isolation oxide films 15, 15 formed in a Si substrate 1.
That is to say, two source/drain regions 9 are selectively formed in the surface of the transistor formation region of the Si substrate 1, a gate insulating film 2 is formed on the channel region between the source/drain regions 9, 9 in the Si substrate 1, a gate electrode 3 is formed on the gate insulating film 2, and side walls 16 are formed on the sides of the gate electrode 3.
The gate electrode 3 is composed of a polysilicon, layer 4 and a silicide layer 11 formed on top of it. Extension regions 8 extend under the side walls 16 from the source/drain regions 9 and silicide regions 10 are formed on the source/drain regions 9.
The gate insulating film 2 is formed of an oxide film or an oxynitride film or a stacked layer thereof. While the gate electrode 3 is mainly formed of the polysilicon layer 4 in the example of FIG. 30, it may be formed by using amorphous silicon as a constituent material.
 less than Manufacturing Method greater than 
A method for manufacturing the MOS transistor structured as shown in FIG. 30 is now described.
First, the Si substrate 1 is sectioned with an element isolation structure, such as trench isolation using the element isolation oxide films 15. Subsequently the entire surface of the Si substrate 1 is thermally oxidized to form the gate insulating film 2. The polysilicon layer 4 is then laid on the gate insulating film 2.
Next, an oxide film of TEOS etc. is formed as a hard mask on the polysilicon layer 4 and is patterned by photolithography. Next, the polysilicon layer 4 is anisotropically etched by using the patterned oxide film as a mask (hard mask) to form the gate.
Then an impurity ion implantation is applied by using the gate-shaped polysilicon layer 4 as a mask to form impurity diffusion regions (the extension regions 8 and source/drain regions 9) and the side walls 16 are formed on the sides of the gate-shaped polysilicon layer 4. In this process, the impurity diffusion regions under the side walls 16 form the extension regions 8.
Next, an impurity ion implantation is applied by using the gate-shaped polysilicon layer 4 and the side walls 16 as masks to form the source/drain regions 9 adjoining the extension regions 8.
Subsequently the oxide film as a hard mask is etched to expose the top surface of the gate-shaped polysilicon layer 4 and then a metal such as cobalt is applied to the entire wafer surface, which is followed by annealing.
Then silicidation occurs in the upper part of the gate-shaped polysilicon layer 4 and in the upper part of the source/drain regions 9 to form the silicide layer 11 and silicide regions 10. Unreacted metal is removed by wet etching.
The MOS transistor structure shown in FIG. 30 is thus completed through the above-described processes. Then a semiconductor device containing the MOS transistor is completed through formation of interlayer insulating films not shown in FIG. 30, interconnecting process, etc.
For newer generations of semiconductor devices containing MOS transistors as shown in FIG. 30, there is an increasing necessity to reduce the power consumption by lowering the power-supply voltage and to enhance the driving current.
That is to say, lowering the power consumption and increasing the speed of semiconductor devices with MOS transistors require lowering the power-supply voltage and increasing the driving current, which have conventionally been realized mainly by reducing the thickness of the SiO2 gate insulating films (i.e. gate insulating films made of SiO2) in the MOS transistors.
FIG. 31 is an explanation diagram showing the off-operation state of the MOS transistor shown in FIG. 30, where the MOS transistor is constructed as an NMOS structure. As shown in this diagram, a source terminal 12 is provided on one of the two source/drain regions 9 (silicide regions 10) and a drain terminal 13 is provided on the other. A gate terminal 14 is provided on the gate electrode 3 and a substrate potential terminal 17 is provided on the Si substrate 1. The source terminal 12, gate terminal 14 and substrate potential terminal 17 are set at a potential of 0 V and the drain terminal 13 is set at a potential of 1.5 V.
When the SiO2 gate insulating film is thinned to a film thickness of 3 nm or smaller, then direct tunneling through the gate insulating film 2 will cause serious gate leakage current I1 as shown in FIG. 31. The gate leakage current I1 may become almost equal to or higher than the leakage current 12 through the normal channel and then it cannot be neglected. That is to say, the standby power (the power in standby state) of the LSI becomes high over the negligible level; the performance of the transistors cannot be further enhanced by thinning the gate insulating films.
As described above, in achieving lower power consumption and higher operation speed of the MOS transistors, the use of SiO2 as a material of the gate insulating films is reaching a limit and attempts are being made to obtain materials and structures of the gate insulating films which can overcome this problem. In such attempts, high dielectric constant materials having higher dielectric constants than SiO2, such as HfO2, ZrO2, etc., are regarded as likely candidates since these materials are less reactive to the Si substrate in which the MOS transistors are fabricated.
However, it is known that, even when a high dielectric constant material as shown above is used to form the gate insulating film, it reacts with the Si substrate in high temperature processing performed after formation of the gate insulating film and thus forms an oxide film between the Si substrate and itself. The oxide film formed between the Si substrate and the high dielectric constant material reduces the dielectric constant of the gate capacitor structure which has attained large capacitance through the use of the high dielectric constant material. Furthermore, the oxide film obtained by the interface reaction with the Si substrate is uneven rather than flat, which reduces the mobility of carries in the channel formed in the Si substrate under the gate insulating film, thus reducing the driving current.
A first aspect of the present invention is directed to a semiconductor device which includes an insulated-gate transistor fabricated in a silicon substrate, the transistor comprising a gate insulating film selectively formed on the silicon substrate, the surface of the silicon substrate under the gate insulating film being defined as a channel region, a gate electrode formed of polysilicon on the gate insulating film, and first and second source/drain regions formed in the surface of the silicon substrate with the channel region interposed therebetween, wherein the gate insulating film contains a material having a higher dielectric constant than silicon oxide film and the gate insulating film comprises an upper part, a center part and a lower part, and wherein the lower part is less reactive with the silicon substrate than the center part is and the upper part is less reactive with the gate electrode than the center part is.
Preferably, according to a second aspect, in the semiconductor device, the gate insulating film has first to third high dielectric constant insulating films each having a dielectric constant higher than that of silicon oxide film and the first to third high dielectric constant insulating films are stacked in the first to third order, the lower part includes the first high dielectric constant insulating film, the center part includes the second high dielectric constant insulating film, and the upper part includes the third high dielectric constant insulating film.
Preferably, according to a third aspect, in the semiconductor device, the transistor includes first and second transistors, the first and second transistors each having the gate insulating film, the gate electrode and the first and second source/drain regions, and the gate insulating film of the first transistor is thicker than the gate insulating film of the second transistor.
Preferably, according to a fourth aspect, in the semiconductor device, a first gate insulating film being the gate insulating film of the first transistor has an insulating film and first to third high dielectric constant insulating films each having a higher dielectric constant than silicon oxide film, and the insulating film and the first to third high dielectric constant insulating films are stacked in this order, wherein the lower part of the first gate insulating film includes the insulating film and the first high dielectric constant insulating film, the center part of the first gate insulating film includes the second high dielectric constant insulating film, and the upper part of the first gate insulating film includes the third high dielectric constant insulating film, a second gate insulating film being the gate insulating film of the second transistor has fourth to sixth high dielectric constant insulating films each having a higher dielectric constant than silicon oxide film, and the fourth to sixth high dielectric constant insulating films are stacked in the fourth to sixth order, wherein the lower part of the second gate insulating film includes the fourth high dielectric constant insulating film, the center part of the second gate insulating film includes the fifth high dielectric constant insulating film, and the upper part of the second gate insulating film includes the sixth high dielectric constant insulating film.
Preferably, according to a fifth aspect, in the semiconductor device, the first and fourth high dielectric constant insulating films are composed of the same material, the second and fifth high dielectric constant insulating films are composed of the same material, and the third and sixth high dielectric constant insulating films are composed of the same material.
A sixth aspect is directed to a method for manufacturing a semiconductor device which includes an insulated-gate transistor fabricated in a silicon substrate. According to the sixth aspect, the semiconductor device manufacturing method comprises the steps of: (a) selectively forming a gate insulating film on the silicon substrate, the surface of the silicon substrate under the gate insulating film being defined as a channel region; (b) forming a gate electrode made of polysilicon on the gate insulating film; (c) forming first and second source/drain regions in the surface of the silicon substrate with the channel region interposed therebetween, wherein the first and second source/drain regions, the gate insulating film and the gate electrode define the transistor, wherein the gate insulating film is formed by using a material having a higher dielectric constant than silicon oxide film, the gate insulating film comprising an upper part, a center part and a lower part, the lower part is less reactive with the silicon substrate than the center part is, and the upper part is less reactive with the gate electrode than the center part is.
Preferably, according to a seventh aspect, in the semiconductor device manufacturing method, the gate insulating film includes first to third high dielectric constant insulating films having a higher dielectric constant than silicon oxide film, the lower part includes the first high dielectric constant insulating film, the center part includes the second high dielectric constant insulating film, and the upper part includes the third high dielectric constant insulating film, the step (a) comprising the steps of (a-1) forming the first high dielectric constant insulating film on the silicon substrate, (a-2) forming the second high dielectric constant insulating film on the first high dielectric constant insulating film, and (a-3) forming the third high dielectric constant insulating film on the second high dielectric constant insulating film.
Preferably, according to an eighth aspect, in the semiconductor device manufacturing method, the transistor includes first and second transistors formed in first and second formation regions in the silicon substrate, the first and second transistors each having the gate insulating film, the gate electrode and the first and second source/drain regions, wherein the step (a) includes a step of forming the gate insulating film of the first transistor thicker than the gate insulating film of the second transistor.
Preferably, according to a ninth aspect, in the semiconductor device manufacturing method, a first gate insulating film being the gate insulating film of the first transistor has an insulating film and first to third high dielectric constant insulating films having a higher dielectric constant than silicon oxide film, wherein the lower part of the first gate insulating film includes the insulating film and the first high dielectric constant insulating film, the center part of the first gate insulating film includes the second high dielectric constant insulating film, and the upper part of the first gate insulating film includes the third high dielectric constant insulating film, and a second gate insulating film being the gate insulating film of the second transistor has fourth to sixth high dielectric constant insulating films having a higher dielectric constant than silicon oxide film, wherein the lower part of the second gate insulating film includes the fourth high dielectric constant insulating film, the center part of the second gate insulating film includes the fifth high dielectric constant insulating film, and the upper part of the second gate insulating film includes the sixth high dielectric constant insulating film, the step (a) comprising the steps of (a-1) forming the insulating film on the first formation region, (a-2) forming the first high dielectric constant insulating film on the insulating film, (a-3) forming the second high dielectric constant insulating film on the first high dielectric constant insulating film, (a-4) forming the third high dielectric constant insulating film on the second high dielectric constant insulating film, (a-5) forming the fourth high dielectric constant insulating film on the second formation region, (a-6) forming the fifth high dielectric constant insulating film on the fourth high dielectric constant insulating film, and (a-7) forming the sixth high dielectric constant insulating film on the fifth high dielectric constant insulating film.
Preferably, according to a tenth aspect, in the semiconductor device manufacturing method, the first and fourth high dielectric constant insulating films are formed of the same material, the second and fifth high dielectric constant insulating films are formed of the same material, the third and sixth high dielectric constant insulating films are formed of the same material, the steps (a-2) and (a-5) are simultaneously performed, the steps (a-3) and (a-6) are simultaneously performed, and the steps (a-4) and (a-7) are simultaneously performed.
As described above, in the transistor of the semiconductor device according to the first aspect of the invention, the gate insulating film contains a material having a higher dielectric constant than a silicon oxide film. Therefore the dielectric constant of the gate capacitor structure composed of the gate electrode, gate insulating film and channel region can be set higher than when the gate insulating film is composed of a silicon oxide film.
In addition, the upper part of the gate insulating film has lower reactivity to the gate electrode than the center part does and the lower part has lower reactivity to the silicon substrate than the center part does. This prevents interface reaction between the upper part and the gate electrode and between the lower part and the silicon substrate, thereby preventing reduction in the dielectric constant of the gate capacitor structure and reduction in the mobility of carriers in the channel.
As a result, the semiconductor device of the first aspect offers a transistor whose gate electrode is composed of polysilicon and which can operate at high speed even at lower power-supply voltages, thus achieving lower power consumption and higher speed operation.
According to the transistor of the semiconductor device of the second aspect, a stacked structure is formed of the first to third high dielectric constant insulating films each having a higher dielectric constant than a silicon oxide film. It is thus possible to relatively easily obtain a gate insulating film whose dielectric constant is higher than that of silicon oxide film and in which the reactivity to the silicon substrate and the gate electrode is lower in the lower and upper parts than in the center part.
According to the semiconductor device of the third aspect, the gate insulating film of the first transistor has a larger film thickness than the gate insulating film of the second transistor. Therefore the structure of the first transistor is more suitable for high voltage operation than the second transistor, so that the transistors can be properly used in suitable voltage ranges; e.g. the first transistor can be used for operation at higher voltage and the second transistor can be used for operation at lower voltage.
According to the first transistor of the semiconductor device of the fourth aspect, a stacked structure is formed of an insulating film and the first to third high dielectric constant insulating films each having a higher dielectric constant than a silicon oxide film. It is thus possible to relatively easily obtain a gate insulating film whose dielectric constant is higher than that of silicon oxide film and in which the lower and upper parts are less reactive than the center part with the silicon substrate and the gate electrode.
Similarly, the second transistor has a stacked structure of the fourth to sixth high dielectric constant insulating films each having a higher dielectric constant than a silicon oxide film. It is thus possible to relatively easily obtain a gate insulating film whose dielectric constant is higher than that of silicon oxide film and which is less reactive with the silicon substrate and the gate electrode in the lower and upper parts than in the center part.
According to the semiconductor device of the fifth aspect, it is possible to simultaneously form the first and fourth high dielectric constant insulating films, the second and fifth high dielectric constant insulating films, and the third and sixth high dielectric constant insulating films. This offers a simple manufacturing process.
In a transistor manufactured by the semiconductor device manufacturing method of the sixth aspect of the invention, the gate insulating film contains a material having a higher dielectric constant than silicon oxide film, so that the dielectric constant of the gate capacitor structure of the gate electrode, gate insulating film and channel region can be set higher than when the gate insulating film is made of a silicon oxide film.
In addition, the upper part of the gate insulating film is less reactive with the gate electrode than the center part and the lower part is less reactive with the silicon substrate than the center part. This prevents the problem that interface reaction between the upper part and the gate electrode or between the lower part and the silicon substrate reduces the dielectric constant of the gate capacitor structure and the mobility of carriers in the channel.
As a result, the semiconductor device manufacturing method of the sixth aspect can manufacture a semiconductor device comprising a transistor whose gate electrode is composed of polysilicon and which can operate at high speed even at lower power-supply voltage, thus achieving lower power consumption and higher speed operation.
According to the semiconductor device manufacturing method of the seventh aspect, it is possible to relatively easily obtain, through the relatively easy process of the steps (a-1) to (a-3), a gate insulating film which has a higher dielectric constant than silicon oxide film and in which the reactivity to the silicon substrate and the gate electrode is lower in the lower and upper parts than in the center part.
According to the semiconductor device manufacturing method of the eighth aspect, the step (a) forms the gate insulating film of the first transistor thicker than the gate insulating film of the second transistor, so that the structure of the first transistor is more suitable for high voltage operation than the second transistor. The method thus provides a semiconductor device in which the transistors can be properly used in suitable voltage ranges; e.g. the first transistor can be used for higher voltage operation and the second transistor can be used for lower voltage operation.
According to the semiconductor device manufacturing method of the ninth aspect, it is possible to relatively easily obtain, through the relatively easy process of the steps (a-1) to (a-4), the gate insulating film of the first transistor which has a higher dielectric constant than silicon oxide film and which has the lower and upper parts less reactive with the silicon substrate and the gate electrode than the center part.
Similarly, it is possible to relatively easily obtain, through the relatively easy process of the steps (a-5) to (a-7), the gate insulating film of the second transistor which has a higher dielectric constant than silicon oxide film and Which has the lower and upper parts less reactive than the center part with the silicon substrate and the gate electrode.
In addition, the first gate insulating film of the first transistor can be formed thicker by the thickness of the insulating film than the second gate insulating film of the second transistor through the easy process of forming the first to third high dielectric constant insulating films and the fourth to sixth high dielectric constant insulating films to approximately equal total film thickness.
According to the semiconductor device manufacturing method of the tenth aspect, the steps (a-2) and (a-5), the steps (a-3) and (a-6) and the steps (a-4) and (a-7) can be simultaneously carried out to simplify the manufacturing process.
The present invention has been made to solve the aforementioned problem and an object of the present invention is to obtain a semiconductor device which contains an insulated-gate transistor which operates at high speed with low power consumption and a manufacturing method thereof.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following: detailed description of the present invention when taken in conjunction with the accompanying drawings.